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EM MICROELECTRONIC-MARIN SA -
V6150
Power Surveillance and Software Monitoring
Features
n Standby mode, maximum current 45 mA n Reset output guaranteed for V DD voltage down to 1.2 V n Comparator for voltage monitoring, voltage reference 1.5 V n Programmable reset voltage monitoring n Programmable power-on reset (POR) delay n Watchdog with programmable time window guarantees a minimum time and a maximum time between software clearing of the watchdog n Time base accuracy 10% n System enable (EN) output offers added security n TTL / CMOS compatible n -40 to +85 C temperature range n On request extended temperature range, -40 to +125 C n DIP8 and SO8 packages
Typical Operating Configuration
Version 00: Version 01:
VDD V6150 R VIN TCL VSS RES EN GND 100 nF
Description
The V6150 offers a high level of integration by voltage monitoring and software monitoring in an 8 lead package. A comparator monitors the voltage applied at the VIN input comparing it with an internal 1.5 V reference. The power-on reset function is initialized after VIN reaches 1.5 V and takes the reset output inactive after T depending of external resistance. The reset POR output goes active low when the VIN voltage is less than 1.5 V. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If the software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system.
Fig. 1
Pin Assignment
DIP8 / SO8
EN RES TCL VSS V6150
VIN R VDD NC
Applications
n n n n n Automotive systems Cellular telephones Security systems Battery powered products Industrial electronics
Fig. 2 1
V6150
Absolute Maximum Ratings
Parameter Maximum voltage at V DD Minimum voltage at V DD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions Symbol Conditions VDDmax VDDmin VMAX VMIN TSTO VSmax TSmax VSS + 7 V VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V -65 to+150 C 1000 V 250 C x 10 s operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Symbol Min. Typ. Max. Units +125 s C -40 Operating temperature TA 2) 5.5 1.2 VDD Supply voltage V RES & EN guaranteed3) VDD 1.2 V Comparator input 0 VDD VIN voltage V RC-oscillator 10 1000 k R programming
1)
Parameter
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Table 2
1)
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper
2) 3)
The maximum operating temperature is confirmed by sampling at initial device qualification. In production, all devices are tested at +85 C. On request devices tested at +125 C can be supplied. A 100 nF decoupling capacitor is required on the supply voltage VDD for stability. RES and EN (EN only for version 00) must be pulled up externally to VDD even if they are unused. (Note: RES and EN are used as inputs by EM test.)
Electrical Characteristics
V DD = 5 V 10%, C = 100 nF, TA = -40 to +85 C, unless otherwise specified
Parameter Supply current in standby mode Supply current RES and EN Output Low Voltage
Symbol ISS ISS
Test Conditions REXT = don't care, TCL = V DD, VIN = 0 V REXT = 100 k, I/Ps at V DD , O/Ps 1 M to VDD VDD = 4.5 V, IOL = 20 mA VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA VDD = 4.5 V, IOH = -1mA VDD = 2.0 V, IOH = -100 A VDD = 1.2 V, IOH = -30 A
Min.
Typ. 23 75 0.4 0.2 0.2 0.06
Max. 45 120
Units A A V V V V V V V
EN (vers. 01) Output High Voltage TCL and VIN TCL Input Low Level TCL Input High Level Leakage current TCL input VIN input resistance Comparator reference 1) Comparator hysteresis1)
1)
VOL VOL VOL VOL VOH VOH VOH VIL VIH ILI RVIN VREF VREF VREF VHY
0.4 0.4 0.2
3.5 1.8 1.0 VSS 2.0
4.1 1.9 1.1 0.8 VDD 1 1.566 1.620 1.620
VSS VTCL VDD VDD = 5 V,TA = +25 C VDD = 5 V VDD = 5 V,-40 C TA +125 C 1.474 1.436 1.420
0.05 100 1.52 2
V V A M V V V mV Table3
The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage plus the comparator hysteresis (see Fig. 5).
2
V6150
ISS Standby versus Temperature at VDD = 5 V 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10
ISS [A]
-40
-30
-20
-10
0
10
20 30 TA [C]
40
50
60
70
80 Fig. 3
Timing Characteristics
V DD = 5.0 V 3%, C = 100 nF, TA = -40 to +85 C, unless otherwise specified
Parameter Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width
Symbol TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL
Test Conditions
Min.
Typ. 250 5 30 100 100 0.2 TWD 0.8 TWD 80 0.4 TWD 40 TWD / 40 2.5
Max. 500 20 100 110 110 88 44
Units ns
s
1 Load 10 k, 50 pF REXT = 123 k, 1% REXT = 123 k, 1% REXT = 123 k, 1% REXT = 123 k, 1% REXT = 123 k, 1% 90 90 72 36 150
ns ms ms ms ms ms ns Table 4
Timing Waveforms
Watchdog Timeout Period
TWD = T POR
- OWP - 20%
+ OWP + 20%
Condition: REXT = 123 k
Watchdog timer reset
TCW - closed window 80
TOW - open window t [ms] 100 120 Fig. 4 3
V6150
Voltage Monitoring
VIN VREF Conditions: VDD 3V No timeout VHY
TSEN TSEN TPOR TSEN TPOR TSEN
RES
Fig. 5
Timer Reaction
TCW TCL RES EN TOW TCW TCW+TOW TCW+TOW TTCL TWDR
1 2 3
TOW
Conditions: V IN > VREF after power-up sequence TCW TCW+TOW
3 correct TCL services EN goes active low - Watchdog timer reset
Timeout Fig. 6
Combined Voltage and Timer Reaction
VIN VREF Condition: VDD 3 V
TPOR=TWD TCL
TOW TCW+TOW
TCW
RES EN TCL too early - Watchdog timer reset 4
1 2 3
3 correct TCL service EN goes active low Fig. 7
V6150
Block Diagram
Enable Logic Voltage Reference VREF Comparator
EN
Vers.00
+
VIN
Reset Control
Vers.01
RES
R
Current Controlled Oscillator
Timer TCL
Open drain output RES
Fig. 8
Pin Description
Pin Name 1 EN Function Vers. 00: Open drain active low enable output. EN must be pulled up to V DD even if unused. Vers. 01: Push-pull active low enable output Open drain active low reset output. RES must be pulled up to V DD even if unused Watchdog timer clear input signal GND terminal No connection Voltage supply REXT input for RC oscillator tuning Voltage comparator input Table 5
2 3 4 5 6 7 8
RES TCL VSS NC VDD R VIN
which is equal to the watchdog time TWD (typically 100 ms with an external resistor of 123 kW connected at R pin). The POR delay prevents repeated toggling of RES even if VIN and the INPUT voltage drops out and recovers. The POR delay allows the microprocessor's crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on V IN is typically 5 ms.
Timer Programming
The on-chip oscillator with an external resistor REXT connected between the R pin and VSS (see Fig. 9) allows the user to adjust the power-on reset (POR) delay, watchdog time TWD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD/40). With R EXT = 123 kW, the typical delays are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWDR is 2.5 ms Note the current consumption increases as the frequency increases.
Functional Description
VIN Monitoring
The power-on reset and the power-down reset are generated as a response to the external voltage level on the VIN input. The external voltage level is typically obtained from a voltage divider as shown in Fig. 9. The user defines the external voltage divider to set the desired threshold level for power-on reset and powerdown reset in his system. The internal comparator reference voltage is typically 1.52 V. At power-up the reset output (RES) is held low (see Fig. 5). When VIN becomes greater than VREF, the RES output is held low for an additional power-on reset (POR) delay
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a "closed" window and an "open" window (see Fig. 4) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after the watchdog timer resets and is defined by TCW = TWD - OWP(TWD ). 5
V6150
The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if TWD = 100 ms (actual value) and OWP = 20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms - 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is 10% accurate, software must use the following calculation as the limits for servicing signal TCL during the open window: Related to curves (Fig. 10 to Fig. 20), especially Fig. 19 and Fig. 20, the relation between T and REXT could WD easily be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 20, the coefficient (T WD to R EXT) is 1.155 where R EXT is in kW and TWD in ms. 3. R EXT (typ.) = 26 x 1.155 = 30.0 kW. 4. 26 ms at +25 C
a)
watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. If the software is stuck in a loop which includes the routine to clear the watchdog, then a conventional watchdog would not make a system even though the software is malfunctioning; the V6150 would make a system reset because the watchdog would be cleared too quickly. If no TCL pulse is applied before the closed and open windows expire, RES will start to generate square waves of period - TCW + TO W + TWDR . The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section "Enable - EN Output"). The RES output must be pulled up to VDD even if the output is not used by the system (see Fig. 9).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 7. On power-up, when the voltage at VIN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on-reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 ms, overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The V6150 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (i.e. the system has correctly restarted after a reset condition). For the version 00 the EN output must be pulled up to VDD even if the output is not used by the system (see Fig.9).
(26 - 10% = 23.4 ms) (26 + 10% = 28.6 ms) a) (28.6 + 5% = 30.0 ms)b)
b)
(23.4 - 5% = 22.2 ms)
min.: (30.0 - 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of (24.0 + 26.7) / 2 = 25.4 ms The ratio between TWD = 26 ms and the (TCL period)= 25.4 ms is 0.975. Then the relation over the production and the full temperature range is, TCL period = 0.975 x TWD or 0.975 x R EXT TCL period = 1.155 , as typical value. a) While PRODUCTION value unknown for the customer when R EXT 123 kW. b) While operating TEMPERATURE range -40 C TA +85 C. 5. If you fixed a TCL period = 26 ms 26 x 1.155 REXT = 30.8 kW. 0.975 If during your production the TWD time can be measured at TA = +25 C and the mC can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature.
Enable - EN Output
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the processor. If the user's software does not send a pulse to the TCL input within the programmed open window timeout period, a short watchdog RES pulse is generated which is equal to TWD/40 = 2.5 ms typically (see Fig. 6). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the 6
V6150
Typical Application
VDD
Supply voltage 100 nF R1 Address Decoder 100 k
100 k
R 100 k
V6150
VIN TCL
Version 00: Version 01:
P RES R2 Motor EN Controls
VSS
RES EN
GND
Fig. 9
7
V6150
TWD versus Temperature at 5 V
10'000 R = 10 M
TWD versus R at 5 V
10'000
1000
R = 1 M
1000
TWD [ms]
100
TWD [ms]
R = 100 k
100
10
R = 10 k
10
-40 C -20 C +25 C +70 C +85 C
R = 1 k 1 -40 -20 +20 +40 +60 +80 Fig. 10 1 0.1 1 10 100 1000 10'000 Fig. 11
0
TA [C]
R [k]
TWD versus V DD at TA = +25 C
10'000 R = 10 M
TWD versus R at TA = +25 C
10'000
1000
R = 1 M
1000
TWD [ms]
TWD [ms]
100
R = 100 k
100
10
R = 10 k
10
R = 1 k 1 3 4 VDD [V] 5 6 Fig. 12 1 0.1 1 10 100
3V 4.8 V 5V 5.2 V 6V
1000 10'000 Fig. 13
R [k]
8
V6150
TWD versus R at TA = +25 C
10'000
1000
100
TWD [ms]
10
3V 4.8 V 5V 5.2 V 6V
1 0.1 1 10 R [k] 100 1000 10'000
Fig. 14
9
V6150
TWD versus V DD at TA = +85 C
10'000 R = 10 M
TWD versus R at TA = +85 C
10'000
1000
R = 1 M
1000
TWD [ms]
TWD [ms]
100
R = 100 k
100
10
R = 10 k
10
R = 1 k 1 3 4 VDD [V] 5 6 Fig. 15 1 0.1 1 10 100 R [k]
3V 4.8 V 5V 5.2 V 6V
1000 10'000 Fig. 16
TWD versus V DD at TA = - 40 C
10'000 R = 10 M
TWD versus R at TA = - 40 C
1000
R = 1 M
1000
100 TWD [ms] 100 TWD [ms] R = 100 k
10
10
R = 10 k 1 R = 1 k
3V 4.8 V 5V 5.2 V 6V
1
3
4 VDD [V]
5
6 Fig. 17
0.1 0.1
1
10
100
1000 10'000 Fig. 18
R [k]
10
V6150
TWD Coefficient versus REXT at TA = +25 C
0.96 0.94 0.92 0.90 TWD Coefficient 0.88 0.86 0.84 0.82 0.80 0.78 0.76 10 100 REXT [k] 1000 Fig. 19
REXT Coefficient versus TWD at TA = +25 C
1.30 1.28 1.26 1.24 1.22 REXT Coefficient 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 1.04 10 100 TWD [ms] 1000 Fig. 20 11
V6150
Ordering Information
The V6150 is available in the following packages: Industrial temperature range (-40 to +85 C) Type 1) Package V6150 nn 8P DIP8 V6150 nn 8S SO8 When ordering please specify complete part number. Marking on package: Package Marking 1) DIP8 V6150 nn SO8 6150 nn 1) nn stands for the versions 00*,01 * on request Extended temperature range (-40 to +125 C) Type 1) Package V6150 nn X 8P DIP8* V6150 nn X 8S SO8*
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/314
12 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03

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